High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Naoya ONIZAWA, Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Masashi IMAI, Tomohiro YONEDA, Takahiro HANYU
2014 IEICE transactions on information and systems  
Naoya ONIZAWA †a) , Akira MOCHIZUKI † †b) , Members, Hirokatsu SHIRAHAMA † †c) , Nonmember, Masashi IMAI † † †d) , Tomohiro YONEDA † † † †e) , and Takahiro HANYU † †f) , Members SUMMARY This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize
more » ... mance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause datatransmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 μm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (< 10 −20 ).
doi:10.1587/transinf.e97.d.1546 fatcat:xkde57mxwzfyxlrja2jggpm6iu