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High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs
2014
IEICE transactions on information and systems
Naoya ONIZAWA †a) , Akira MOCHIZUKI † †b) , Members, Hirokatsu SHIRAHAMA † †c) , Nonmember, Masashi IMAI † † †d) , Tomohiro YONEDA † † † †e) , and Takahiro HANYU † †f) , Members SUMMARY This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize
doi:10.1587/transinf.e97.d.1546
fatcat:xkde57mxwzfyxlrja2jggpm6iu