A 1 cycle-per-byte XML parsing accelerator

Zefu Dai, Nick Ni, Jianwen Zhu
2010 Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10  
Extensible Markup Language (XML) is playing an increasing important role in web services and database systems. However, the task of XML parsing is often the bottleneck, and as a result, the target of acceleration using custom hardware or multicore CPUs. In this paper, we detail the design of the first complete field programmable gate array (FPGA) accelerator capable of XML well-formed checking, schema validation, and tree construction at a throughput of 1 cycle per byte (CPB). This is a
more » ... ant advancement from 40 CPB, the best previous reported commercial result. We demonstrate our design on a Xilinx Virtex-5 board, which successfully saturates a 1 Gbps Ethernet link.
doi:10.1145/1723112.1723148 dblp:conf/fpga/DaiNZ10 fatcat:f4kgjzc4bvd3vjspjbhmbb67bi