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High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain
2014
2014 12th IEEE International Conference on Embedded and Ubiquitous Computing
High-Level Synthesis (HLS) is an automated design process that deals with the generation of behavioral hardware descriptions from high-level algorithmic specifications. The main benefit of this approach is that ever-increasing system-on-chip (SoC) design complexity and ever-shorter time-to-market can still be both manageable and achievable. This advantage, coupled with the increasing number of available heterogeneous platforms that loosely couple general-purpose processors with
doi:10.1109/euc.2014.28
dblp:conf/euc/NaneSPGB14
fatcat:elr5fcxj6bec7btbpuywsvnfnq