Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias

Hector Villacorta, Jose Garcia-Gervacio, Victor Champac, Sebastia Bota, Jaime Martinez, Jaume Segura
2013 2013 14th Latin American Test Workshop - LATW  
Bridge defects are an important manufacturing defect that may escape test. Even more, it has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods. Therefore, ad vances in test methodologies to deal with nanometer issues are required. In this work the feasibility of using Low VDD and body bias in a delay based test to detect resistive bridge defects in CMOS nanometer circuits is analyzed. The detection of bridge defects using a
more » ... based test in nanometer circuits is strongly influenced by: 1) spatial correlation of the process parameters such as length, width and oxide thickness of the transistor, (2) random placement of dopants, and (3) the signal correlation due to reconvergent paths. Because of this, in this work a Statistical Timing Analysis Framework (STAF) is used to analyze the possibilities of detection of bridge defect using a delay based test. The STAF considers different values of VDD and body bias. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage that gives a more realistic measure of the degree of detection of the defect. This methodology is applied to some ISCAS benchmark circuits implemented in a 65nm CMOS technology. The obtained results show the feasibility of the proposed methodology.
doi:10.1109/latw.2013.6562671 dblp:conf/latw/VillacortaGCBMS13 fatcat:ri2nviahbrhrrkncrpd7wjdogq