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Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias
2013
2013 14th Latin American Test Workshop - LATW
Bridge defects are an important manufacturing defect that may escape test. Even more, it has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods. Therefore, ad vances in test methodologies to deal with nanometer issues are required. In this work the feasibility of using Low VDD and body bias in a delay based test to detect resistive bridge defects in CMOS nanometer circuits is analyzed. The detection of bridge defects using a
doi:10.1109/latw.2013.6562671
dblp:conf/latw/VillacortaGCBMS13
fatcat:ri2nviahbrhrrkncrpd7wjdogq