Dynamic Partial Reconfiguration Implementation of AES Algorithm

Snehal Wankhade, Rashmi Mahajan
2014 International Journal of Computer Applications  
This work reports Partial Reconfiguration (PR) by which selected areas of an FPGA can be reconfigured during runtime. Today cryptographic algorithms are not safe also embedded cryptographic hardware is costly. Hence to make it cost effective and to provide more secureness reconfigurable hardware such as FPGA is used with the concept of partial reconfiguration. This work gives briefings about the method of hardware implementation for AES encryption algorithm with Dynamic reconfigurable keys. Our
more » ... implementation reaches very good efficiencies than the compared one as we have adopted our own methodology for key expansion. With the combination of adopted methodology & used FPGA this paper shows better agreement as compared to previous work. This implementation could be a good solution to preserve confidentiality and convenience to the information in the numeric communication.
doi:10.5120/16986-7084 fatcat:ekaw3wn4wbfjfgtyjb5n6vwjtm