A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is
International Journal of Latest Engineering Research and Applications (IJLERA)
In Integrated circuits a gargantuan portion of chip power is expended by clocking system which comprises of timing elements such as flipflops, latches and clock distribution network. This paper enumerates power efficient design of shift registers using D flipflops along with Clock and Power gating integration. Clock gating and power gating proves to be very effective solutions for reducing dynamic and active leakage power respectively. The two techniques are coupled in such a way that the clockfatcat:z7ybiexdpjgzvcenme5ycr2nmy