Reduction of Power Dissipation on Network-On-Chip Using Efficient Data Encoding and Decoding Techniques

P Manoj Kumar, M Kishore Babu
International Journal of Recent Trends in VLSI,Embedded Systems and Signal Processing   unpublished
Network-on-Chip(NoC) has become default communication paradigm in System-on-Chip (SoC). NoC is a scalable and modular design approach. It improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs. The success of the NoC design depends on the research of the interfaces between processing elements of NoC and interconnection fabric. In NoC links are the major power dissipation sources. Self and coupling-switching activities are responsible for link power
more » ... ble for link power dissipation. This paper introduces 3-bit coupling transition data encoding and decoding schemes for reduction of link power dissipation and delay. This paper analyzes the power and delay reduction of both encoding and decoding schemes in Xilinx.
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