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FPGA based tester tool for hybrid real-time systems
2008
Microprocessors and microsystems
This paper presents a design methodology for a hybrid Hardwarein-the-Loop (HIL) tester tool, based on both discrete event system theory, given by timed automata, and continuous systems theory, given by difference equations. It is implemented using an FPGA platform that guarantees speed enhancement, time accuracy and extensibility with no performance loss. We have focused on the implementation of a discrete event system, specifically timed automata into FPGA, and we have linked them with
doi:10.1016/j.micpro.2008.07.003
fatcat:eon56z7qnbdxbl45anv6f33wti