Economics and design challenges in implementing CMOS Transimpedance Amplifers for 10Gb/s operation

Ty Yoon
2009 2009 14th OptoElectronics and Communications Conference  
This paper examines the technological challenges in implementing 10Gb/s Transimpedance Amplifiers in standard CMOS process technology. Circuit techniques for enabling 10Gb/s CMOS circuit operation are discussed. Paper concludes with measurements results for an actual 10Gb/s CMOS Transimpedance Amplifier.
doi:10.1109/oecc.2009.5221591 fatcat:7mp3ijjlxbbnzfbhgonfwv3l3e