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Abstraction and Refinement Techniques in Automated Design Debugging
2006
International Workshop on Microprocessor Test and Verification
Verification is a major bottleneck in the VLSI design flow with the tasks of error detection, error localization, and error correction consuming up to 70% of the overall design effort. This work proposes a departure from conventional debugging techniques by introducing abstraction and refinement during error localization. Under this new framework, existing debugging techniques can handle large designs with long counter-examples yet remain run time and memory efficient. Experiments on benchmark
doi:10.1109/mtv.2006.1
dblp:conf/mtv/SafarpourV06
fatcat:hrxgf2fdovetzmtk2crdtraclu