A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2003; you can also visit the original URL.
The file type is
2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233)
State space traversal algorithms for Finite State Machine (FSM) models of synchronous sequential circuitry are used extensively in various formal verification approaches such as Equivalence Checking (EC) and model checking. Symbolic Binary Decision Diagram (BDD) based approaches have allowed many FSM models to be verified due to the compact representations they provide. However, there still remain circuits for which the traversal cannot be carried out due to the size of the Transition Relationdoi:10.1109/pacrim.2001.953681 fatcat:757idm44gjcztn6mw4cbpt2o3e