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Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method
2008
2008 9th International Conference on Solid-State and Integrated-Circuit Technology
This paper studies various Double-Gate (DG) FinFET structures optimized for better "off state" and "on state" performance. In this work, we study the impact of process variation on the performance of DG-FinFET device with 20nm gate length. This was achieved through calibrated TCAD simulations. We show that the spacer thickness variation has the highest impact on Ion of the DG-FinFETs. In this work, we also have demonstrated the suitability of method of Plackett-Burman Design of Experiments
doi:10.1109/icsict.2008.4734510
fatcat:hbgbcuhfjremlhnkec42ykks2i