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LEAKAGE POWER REDUCTION OF ASYNCHRONOUS PIPELINES
2011
Journal of Circuits, Systems and Computers
With CMOS technology scaling, leakage power is expected to become a significant portion of the total power. Dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications. This paper presents dual-threshold voltage technique for reducing leakage power dissipation of Quasi Delay Insensitive asynchronous pipelines while still maintaining high performance of these circuits. We exploited
doi:10.1142/s0218126611007207
fatcat:44ext2mvrjcfjpigwxqyws3p7e