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The VHDL based design of the MIDA MPEG1 audio decoder
Proceedings of EURO-DAC. European Design Automation Conference
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This paper describes the features and design methodology of MIDA, a MPEG1 integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL descriptions, and has been implemented using a cell based approach and a 0.7 µm, 2 metal layers CMOS technology. The die area is 95 mm 2 . Synthesis tools have also been used for automatic insertion of test structures and automatic test pattern generation.
doi:10.1109/eurdac.1995.527464
dblp:conf/eurodac/FinotelloP95
fatcat:qhfqib5a2jeflf7bmxzy5fkine