Analyzing Fair Parametric Extended Automata [chapter]

Ahmed Bouajjani, Aurore Collomb-Annichini, Yassine Lakhnech, Mihaela Sighireanu
2001 Lecture Notes in Computer Science  
We address the problem of verifying safety and liveness properties for in nite-state systems, using symbolic reachability analysis. The models we consider are fair parametric extended automata, i.e., counter automata with parametric guards, supplied with fairness conditions on their transitions. In previous work, we shown that symbolic reachability analysis using acceleration techniques can be used to generate nite abstractions (symbolic graphs) of the original in nite-state model. In this
more » ... , we show that this analysis can be also used to introduce fairness conditions on the generated abstract model allowing to model-check liveness properties. We show rst how to translate faithfully the fairness conditions of the in nite-state original model to conditions on the generated nite symbolic graph. Then, we show that we can also synthesize automatically new fairness conditions allowing to eliminate in nite paths in the symbolic graph which do not correspond to valid behaviours in the original model. These in nite paths correspond to abstractions of boundedly iterable (nested) loops. We show techniques allowing to decide this bounded iterability for a class of components in the symbolic graph. We illustrate the application of these techniques to nontrivial examples.
doi:10.1007/3-540-47764-0_19 fatcat:fpujrtbburduvlrfxvsfj2jwr4