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This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 2400-transistor circuit, anddoi:10.1145/224081.224109 dblp:conf/islped/TachibanaKNKYMG95 fatcat:4546igmcdfcrnes6zezgtgrzvm