Power and area optimization by reorganizing CMOS complex gate circuits

M. Tachibana, S. Kurosawa, R. Nojima, N. Kojima, M. Yamada, T. Mitsuhashi, N. Goto
1995 Proceedings of the 1995 international symposium on Low power design - ISLPED '95  
This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 2400-transistor circuit, and
more » ... succeeded in reducing the transistor count by 12%, and the net count by 13%. Transistor sizing and layout compaction reduced the average transistor size by one eighth, while the same delay was maintained. Power dissipation was cut to less than half, even when wiring capacitances were dominant.
doi:10.1145/224081.224109 dblp:conf/islped/TachibanaKNKYMG95 fatcat:4546igmcdfcrnes6zezgtgrzvm