Energy-efficient contention-aware application mapping and scheduling on NoC-based MPSoCs

Dawei Li, Jie Wu
2016 Journal of Parallel and Distributed Computing  
h i g h l i g h t s • Energy-efficient application mapping and scheduling for Network-on-Chip systems. • An approach that combines processor voltage scaling and link frequency tuning. • A two-step method that provides clear and organized solution. • Using genetic algorithm to achieve near-optimal voltage and frequency assignment. a b s t r a c t We consider the problem of energy-efficient contention-aware application mapping and scheduling on Network-on-Chip (NoC) based multiprocessors. For an
more » ... pplication represented by a directed acyclic graph, we present a model where voltage scaling techniques for processors can be combined with frequency tuning techniques for NoC links to save overall system energy consumption. We employ a two-step approach to solve the overall mapping and scheduling problem. First, the application mapping problem is formulated as a quadratic binary programming problem, which aims to minimize the communication energy; we apply a relaxation-based iterative rounding algorithm to solve it. With the mapping achieved, we further consider the application scheduling problem, which aims to find the optimal voltage level for each task of the application and optimal frequency level for each communication of the application to minimize the overall system energy consumption, given the application deadline. To attack the second problem, we first design an algorithm based on the earliest time first scheduling to determine the application's finish time if a voltage and frequency assignment is given; then, we develop a genetic algorithm to search the solution space for the voltage and frequency assignment that minimizes the overall system energy consumption and meets the application's deadline. Through these two steps, we produce a mapping and scheduling that meets the application's deadline, and significantly reduces the overall system energy consumption. Experiments are conducted for a number of randomly generated application graphs, as well as several real application graphs to verify the energy reduction and applicability of the proposed model and algorithms. (J. Wu). Energy consumption on these integrated systems has been a critical issue. Previously, energy-aware task scheduling problems have been studied extensively for traditional multiprocessor platforms without the consideration of communication time and energy. Generally speaking, processors are equipped with the capability of Dynamic Voltage and Frequency Scaling (DVFS) [4] . When the processor's utilization is low, it can be put to lower voltage/frequency levels to save energy consumption. For NoCbased MPSoCs, routers and links also consume a large portion of on-chip energy. The integrated routers and links of the Alpha 21 364 processor [21] consume 23 W out of the total chip power of 125 W (20%). Among the 23 W power, 58% of the power is consumed by the links; NoC links consume about 10% of the total http://dx.
doi:10.1016/j.jpdc.2016.04.006 fatcat:q3efcvo7njak5oipa3m7bwtjyi