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Compiler driven architecture design space exploration for DSP workloads: A study in software programmability versus hardware acceleration
2009
2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers
Wireless communications and video kernels contain vast instruction and data level parallelism that can far outstrip programmable high performance DSPs. Hardware acceleration of these bottlenecks is commonly done at the cost of software flexibility. Many vendors, however, view software as intellectual property and prefer a software solution that is a proprietary implementation. The paper uses a research compiler for architectural design space exploration to present comparisons between compiler
doi:10.1109/acssc.2009.5470122
fatcat:6hiqu5mt6jeqvgoxqux56mneqy