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Net-Aware Critical Area Extraction for Opens in VLSI Circuits Via Higher-Order Voronoi Diagrams
2011
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
We address the problem of computing critical area for open faults (opens) in a circuit layout in the presence of multilayer loops and redundant interconnects. The extraction of critical area is the main computational bottleneck in predicting the yield loss of a VLSI design due to random manufacturing defects. We first model the problem as a geometric graph problem and we solve it efficiently by exploiting its geometric nature. To model open faults we formulate a new geometric version of the
doi:10.1109/tcad.2010.2100550
fatcat:x52b6fpw2fdjnenjzla4axzzgm