Cascaded FPGA-based FIR filter for ultrasound imaging applications using the DSP Builder Tool
In this paper, we present the design and implementation of an FPGA-based cascaded digital low-pass FIR filter (DLPF) for raw ultrasound echo signals. The proposed filter design takes advantage of the symmetry proprieties of the conventional FIR filter for reducing the number of multipliers by half. The DLPF was built as a tapped cascaded interconnection of identical FIR subfilters within the Matlab/Simulink environment combined with the DSP Builder toolbox, allowing complete model simulation
... model simulation and automatic hardware description language code generation. In order to evaluate our design, we employed symmetrical 4-tap cascaded FIR filter structures to implement a 16-, 24- and 32-tap DLPF filter, respectively. Assuming a pass band frequency of 3.2 MHz and a stop band frequency of 8 MHz, the accuracy and performance of the DLPF are analyzed for different filter orders, coefficient length and two filter design methods: Equiripple and Least-Squares. The normalized root mean square error (NRMSE) cost function is used for comparison with the reference double-precision floating-point values obtained by FDATool in Matlab. The implementation results demonstrate excellent performance and agreement between the Matlab reference design and the hardware experiments using the FPGA-based system. This methodology can be used as an alternative to accelerate the investigation of new DSP algorithms based on hardware for ultrasound imagining.