Leakage and process variation effects in current testing on future CMOS circuits

A. Keshavarzi, J.W. Tschanz, S. Narendra, V. De, W.R. Daasch, K. Roy, M. Sachdev, C.F. Hawkins
<span title="">2002</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hkpx3vsnhrfb7jh6hlwads7olq" style="color: black;">IEEE Design &amp; Test of Computers</a> </i> &nbsp;
FOR FUTURE CMOS technology generations, supply and threshold voltages will have to scale together to sustain high performance, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements pose several technology, circuit design, and testing challenges. Controlling process variation and leakage has become criti-cal in designing and testing ICs. Die-to-die and intradie parameter variations-which are worsening with technology scaling-affect IC
more &raquo; ... clock frequency and leakage power distributions. These effects are more pronounced at low supply voltages (V CC ). Technology scaling also affects various aspects of VLSI testing. 1 Specifically, elevated transistor leakage and excessive parameter variations in scaled process technologies threaten the feasibility of leakagebased (I DDQ ) tests. Researchers have proposed several methods for adapting I DDQ testing to scaled technologies-reverse body bias (RBB), current signatures, ∆ I DDQ testing, and transient current testing (see the sidebar, "Other I DDQ test methods"). Our data suggests adopting a correlative multiparameter test solution. For high-performance IC applications, we propose looking at leakage in the context of the circuit's maximum operating frequency. This approach doesn't rely on the absolute value of the current. Added parameters of temperature and body bias further improve our test technique's defect detection sensitivity. Leakage averaging and variance Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits Defect-Oriented Testing in the Deep-Submicron Era 36 Barriers to technology scaling, such as leakage and parameter variations, challenge the effectiveness of current-based test techniques. This correlative multiparameter test approach improves current testing sensitivity, exploiting dependencies of transistor and circuit leakage on operating frequency, temperature, and body bias to discriminate fast but intrinsically leaky ICs from defective ones.
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