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As the logic capacity of Field-Programmable Gate Arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components (called bit-slices) which are connected together by regularly structured signals (called buses), it is possible to utilize datapath regularity in order to achieve significant area savings through FPGAdoi:10.1145/1046192.1046194 dblp:conf/fpga/YeR05 fatcat:dx4n4ip3wbd3bnn6btewyvtyle