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Microarchitectural mechanisms to exploit value structure in SIMT architectures
2013
Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13
SIMT architectures improve performance and efficiency by exploiting control and memory-access structure across data-parallel threads. Value structure occurs when multiple threads operate on values that can be compactly encoded, e.g., by using a simple function of the thread index. We characterize the availability of control, memory-access, and value structure in typical kernels and observe ample amounts of value structure that is largely ignored by current SIMT architectures. We propose three
doi:10.1145/2485922.2485934
dblp:conf/isca/KimTSLB13
fatcat:nw23iplrp5ajxftz4vstmq2r3i