A compact digital amplitude modulator in 90nm CMOS

V Chironi, B Debaillie, A Baschirotto, J Craninckx, M Ingels
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm 2 chip area.
doi:10.1109/date.2010.5457112 dblp:conf/date/ChironiDBCI10 fatcat:7thwpukv65emlmecur2cvaxcyy