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Fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and 35 ps jitter

Chao Xu, W. Sargeant, K. Laker, J. van der Spiegel
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)  

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A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency. Disciplines Electrical and Computer Engineering
more » ... mments Abstract A fully integrated phase-locked loop (PLL) fabricated in a 0.24pm, 2 . 5~ digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24um CMOS technology. Also it has very low peak-to-peak jitter less than f35ps at 1.25GHz output frequency.
doi:10.1109/icecs.2001.957665 fatcat:cucwy6twynfwnnjy7fhybecomq
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Chao Xu, W. Sargeant, K. Laker, J. van der Spiegel. "Fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and 35 ps jitter." ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)