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Implementation and evaluation of update-based cache protocols under relaxed memory consistency models
1995
Future generations computer systems
Invalidation-based cache coherence protocols have been extensively studied in the context of large-scale shared-memory multiprocessors. Under a relaxed memory consistency model, most of the write latency can be hidden whereas cache misses still incur a severe performance problem. By contrast, update-based protocols have a potential to reduce both write and read penalties under relaxed memory consistency models because coherence misses can be completely eliminated. The purpose of this paper is
doi:10.1016/0167-739x(94)00067-o
fatcat:w4hucg77hzhgrfson4sjih2rme