Theory of latency-insensitive design

L.P. Carloni, K.L. McMillan, A.L. Sangiovanni-Vincentelli
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Latency-insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The
more » ... al of the protocol is to guarantee that latency-insensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency-insensitive methodology to design large digital integrated circuits by using deep submicrometer technologies. Index Terms-Deep submicrometer design, formal methods, latency-insensitive protocols, system design. I. INTRODUCTION T HE THEORY of latency-insensitive design formally separates communication from computation by defining a system as a collection of computational processes that exchange data by means of communication channels. The communication is governed by an abstract protocol, whose main characteristic is to be insensitive to the latencies of the channels. The theory may be applied as a rigorous basis to design complex digital systems by simply composing predesigned and verified components so that the composition satisfies, formally and "by construction," the required properties of synchronization and communication. In particular, relevant applications may be found in the design of integrated circuits to be implemented with the future generations of process technologies. Indeed, for the so-called deep submicrometer (DSM) technologies (0.1 m and below), where millions of gates will be customary, a design methodology that guarantees by construction that certain key properties are satisfied appears as the only hope to achieve correct designs in short time. Furthermore, the characteristics of DSM designs will exacerbate the timing-closure problem that is already present with the current technologies: the designers Manuscript
doi:10.1109/43.945302 fatcat:jdowtgvwpfbldjsrlgulx6s6jy