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Separation Logic Verification of C Programs with an SMT Solver
2009
Electronical Notes in Theoretical Computer Science
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This paper presents a methodology for automated modular verification of C programs against specifications written in separation logic. The distinguishing features of the approach are representation of the C memory model in separation logic by means of rewrite rules suitable for automation and the careful integration of an SMT solver behind the separation logic prover to guide the proof search.
doi:10.1016/j.entcs.2009.09.057
fatcat:m4qroup4cvgqplzlhhnlecg4qa