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Trading conflict and capacity aliasing in conditional branch predictors
1997
Proceedings of the 24th annual international symposium on Computer architecture - ISCA '97
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardware resources for branch-predictor tables are invariably limited, it is not possible to hold all relevant branch history for all active branches at the same time, especially for large workloads consisting of multiple processes and operating-system code. The problem that results, commonly referred to as aliasing in the
doi:10.1145/264107.264211
dblp:conf/isca/MichaudSU97
fatcat:ahrhri7mg5gulg6xcfe2htk2ey