A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2010; you can also visit the original URL.
The file type is
A chip-level electrostatic discharge simulation strategy
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.
This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chiplevel simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node VDD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.doi:10.1109/iccad.2004.1382593 dblp:conf/iccad/QianKNS04 fatcat:dsnnmntpqfd6dlzy354m5uzf6y