Guest Editors' Introduction: Special Section on Energy Efficient Computing

Mootaz Elnozahy, Rami Melhem
2012 IEEE transactions on computers  
F ROM portable devices to data centers, energy consumption has grown to be a major limitation to usability and performance. Energy cost and associated infrastructure also constitute a growing proportion of the expense of building and running a typical data center. Therefore, energy efficient computing has become an active area of research, motivated further by environmental concerns and a desire to limit the impact of computing on the ecosystem. Unlike many research areas, Energy efficient
more » ... ting involves all system's components and design layers. As a result, we often see that specialized forums tend to address only one aspect of the research area, and there isn't a single forum that adequately covers the large span of topics that touch on power aware computing. Hence the idea behind this special issue: We sought to assemble a special issue that is devoted to the topic at large, and without confining the scope to a particular subtopic. As a result of the call for papers, we received a total of 44 submissions to this special section. We handled conflict of interest in the traditional way where each of the editors handled the papers with a conflict of interest of the other editor. We obtained at least three reviews for each paper. Only 12 papers survived the first round of revisions and only one of the twelve papers was accepted with minor revisions. The remaining eleven papers went through major revisions and a second round of reviews. Five papers were accepted after the second round with two papers going through a second major revision, and a third round of reviews, after which they were accepted. In total, eight excellent papers appear in this special section and, although there were no attempts to balance the topics of the accepted papers, the eight papers that made it through the review process represent a wide spectrum of interests within power aware computing. This spectrum includes theory, systems, and practice papers, and encompasses different types of systems including high performance systems, servers, real-time systems, and mobile systems. In what follows, we briefly summarize the contributions of each of the eight papers included in this special section. The paper "Scheduling Precedence Constrained Tasks with Reduced Processor Energy on Multiprocessor Computers," considers the problems of minimizing schedule length with energy consumption constraints and minimizing energy consumption with schedule length constraints. Scheduling tasks to multiprocessors is generally NP complete, and thus adding energy consumption into the mix adds another dimension of complexity to the problems. This complexity is dealt with by decomposing the problems into subproblems that separate precedence constraints, task scheduling and power budget allocation, leading to three types of power allocation and scheduling heuristics, namely, prepower-determination algorithms, postpower-determination algorithms, and hybrid algorithms. The different algorithms are evaluated and compared through simulation. In the paper "Synchronization-Aware Energy Management for VFI-based Multicore Real-Time Systems," the authors investigate scheduling real-time tasks on multicore processors with separate voltage and frequency islands. In addition to the management of computational resources, the authors propose an integrated synchronization-aware framework to appropriately reclaim, preserve, release and steal slack at run time to slow down the execution of tasks within each voltage island, thus reducing the overall energy consumption of the system. Evaluation is also done through simulation. The goal of the paper "Tiered Memory: An Iso-Power Memory Architecture to Address the Memory Power Wall," is to reduce the energy consumption of memory systems. It presents a memory architecture that can support more memory capacity for a limited power budget. The architecture is based on dividing the memory into multiple tiers, each set to a different power mode. A formal model is presented for provisioning a memory that is divided into "hot" and "cold" ranks, where the former are kept active (as normal), and the latter are kept in a low-power state. A cold rank is awakened when sufficiently many accesses to it have accumulated or a time-out threshold for delaying cold accesses is reached. Evaluation assuming server-class systems running many virtual machines show that using two-tiers outperforms the conventional single-tier system for an equivalent power budget. Moving from memory design to processor design, the paper "A Customized Processor for Energy Efficient Scientific Computing," resents and evaluates a novel architecture specifically designed to tackle identified bottlenecks in GPU architectures when running scientific code. The proposed architecture incorporates special features to deal with efficient back-to-back execution of SIMD floating point operations, memory latency, and control divergence in SIMD execution. Specifically, to improvethe power efficiency of dense matrix scientific processors, operations
doi:10.1109/tc.2012.262 fatcat:3v4ej7z5enfadh7rn5fxqmvphy