Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications

Chulho Shin, Peter Grun, Nizar Romdhane, Christopher Lennard, Gabor Madl, Sudeep Pasricha, Nikil Dutt, Mark Noll
2007 Design automation for embedded systems  
The practical application of electronic system-level (ESL) design has been a key challenge of transaction-level modeling (TLM) methodologies in the past few years. While the benefits of ESL are well known, making the investment pay-off has required two key factors to be resolved: the simulation speed of the virtual platform model has to be fast enough to enable software design, and the flow from ESL design to implementation has to be seamless. We introduce two themes to address these issues:
more » ... le-based simulation and a Springer 120 C. Shin et al. the Synopsys coreAssembler tool and Galaxy suite of tools, we show that competent solutions to both of these adoption issues exist in the industry today. Introduction The creation and use of virtual platforms is a developing trend to improve time-to-market for complete embedded systems design. Until a few years ago, designers would often explore designs at the implementation model (or RT) level. While this was possible for designs that were relatively simple, exploring today's complex SoC designs at the RT level is an intimidating prospect. Not only is the RTL simulation speed too slow to allow adequate coverage of the large design space in modern SoC designs, but making small changes in the design can require considerable re-engineering effort due to the highly complex nature of these systems. To overcome these limitations, system designers have been forced to raise the level of abstraction of these models. These high level models, usually captured with high level languages such as C/C++, give an early estimate of the system characteristics before committing to RTL development. They also provide a virtual representation of the system on which embedded software development can commence prior to the availability of silicon [19] [20] [21] . This early-prototyping that has helped optimized architectural exploration, as well as enable the concurrent hardware and software development process, is now a vital part of industrial embedded system design flows. With improved realization of the benefits of system-level design, more IP and systems houses are investing in use of a system level methodology. A rich library of third-party IP simulation models is emerging, and the creation of virtual system platforms is converging to a reuse process. The difficulty here is that models from different providers generally use different scheduling techniques and model interfaces. For example, cycle-based scheduling is a concept in cycle-accurate modeling that can increase the simulation speed without losing clock-cycle accuracy of the system. System-level models can take advantage of the cycle-based abstraction as timing within clock-cycles is not relevant to the system. However, linking from system-level design to traditional hardware development simulations requires the support of event-based simulation as these simulators are built to handle intra-cycle timing. Having to integrate models from multiple sources and scheduling domains has brought new issues to the forefront. In this multi-schedule world, there is the need to handle efficient mixed-level simulation. The key to supporting heterogeneous model integration is the development of standard interfaces, both for cycle, and for event-based models. Beyond the need to address model integration efficiently, the time-to-market advantages of system-level design and virtual prototyping can only be fully exploited with an efficient link to hardware implementation. The libraries of reusable hardware IP that exist as system models should also exist as re-usable RTL components. In practical commercial design flows, there is frequently a need to iterate between system specifications and implementation. The configuration of a system, its component selection, system connectivity, register assignment and memory maps must be consistent between virtual prototypes and the hardware designs if the system validation and software development threads are all to remain aligned. Springer Enabling heterogeneous cycle-based and event-driven simulation
doi:10.1007/s10617-007-9003-x fatcat:ewdww5lwnvc4tinvf5an2fy3ae