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Crosstalk noise optimization by post-layout transistor sizing
2002
Proceedings of the 2002 international symposium on Physical design - ISPD '02
This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of the aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing a crosstalk noise estimation method and a transistor sizing framework which
doi:10.1145/505388.505420
dblp:conf/ispd/HashimotoTO02
fatcat:je5vcrylrrfmxfuzzb6xfrek5e