Crosstalk noise optimization by post-layout transistor sizing

Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of the aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing a crosstalk noise estimation method and a transistor sizing framework which
more » ... re previously developed. Our method exploits the transistor sizing framework that can vary the transistor widths inside cells with interconnects unchanged. Our optimization method therefore never cause a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay increase. These results show that the risk of crosstalk noise problems can be considerably reduced after detailrouting.
doi:10.1145/505388.505420 dblp:conf/ispd/HashimotoTO02 fatcat:je5vcrylrrfmxfuzzb6xfrek5e