Sub-Microwatt Analog VLSI Trainable Pattern Classifier

Shantanu Chakrabartty, Gert Cauwenberghs
2007 IEEE Journal of Solid-State Circuits  
The design and implementation of an analog system-on-chip template-based pattern classifier for biometric signature verification at sub-microwatt power is presented. A programmable array of floating-gate subthreshold MOS translinear circuits matches input features with stored templates and combines the scores into category outputs. Subtractive normalization of the outputs by current-mode feedback produces confidence scores which are integrated for category selection. The classifier implements a
more » ... support vector machine to select programming values from training samples. A two-step calibration procedure during programming alleviates offset and gain errors in the analog array. A 24-class, 14-input, 720-template classifier trained for speaker identification and fabricated on a 3 mm 3 mm chip in 0.5 m CMOS delivers real-time recognition accuracy on par with floating-point emulation in software. At 40 classifications per second and 840 nW power, the processor attains a computational efficiency of 1 3 10 12 multiply-accumulates per second per Watt of power.
doi:10.1109/jssc.2007.894803 fatcat:kwoig46jbvfbdg5zeokfvjjy6a