A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode $\Delta\Sigma$ Receiver

Charles Wu, Elad Alon, Borivoje Nikolic
<span title="">2014</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cz5rf4o3ezafnl4kjpq643g32e" style="color: black;">IEEE Journal of Solid-State Circuits</a> </i> &nbsp;
A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A flat signal transfer function is chosen to support wide-frequency-range radios. A multilevel (two-bit) nonreturn-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier, guarantees a highly linear front end. For a 4 MHz signal, the peak SNDR of the receiver exceeds 68 dB and is better than 60 dB across
more &raquo; ... e 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of 10 dBm is achieved while dissipating only 40 mW from 1.1 V/1.5 V supply voltages. Index Terms-ADC, bandpass ADC, CMOS, ADC, LNTA, receiver, software-defined radio. 0018-9200
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jssc.2014.2319249">doi:10.1109/jssc.2014.2319249</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gnvawn5p7fbm3csnpzje4ntqwu">fatcat:gnvawn5p7fbm3csnpzje4ntqwu</a> </span>
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