A survey of checker architectures

Rajshekar Kalayappan, Smruti R. Sarangi
2013 ACM Computing Surveys  
Reliability is quickly becoming a primary design constraint for high end processors because of the inherent limits of manufacturability, extreme miniaturization of transistors, and the growing complexity of large multicore chips. To achieve a high degree of fault tolerance, we need to detect faults quickly, and try to rectify them. In this paper, we focus on the former aspect. We present a survey of different kinds of fault detection mechanisms for processors at the circuit, architecture, and
more » ... ftware level. We collectively refer to such mechanisms as checker architectures. First, we propose a novel two-level taxonomy for different classes of checkers based on their structure and functionality. Subsequently, for each class we present the ideas in some of the seminal papers that have defined the direction of the area along with important extensions published in later work.
doi:10.1145/2501654.2501662 fatcat:rmmc2ntqofgkvnbjhwpmekol4i