A room-temperature silicon single-electron metal–oxide–semiconductor memory with nanoscale floating-gate and ultranarrow channel

Lingjie Guo, Effendi Leobandung, Stephen Y. Chou
1997 Applied Physics Letters  
We have demonstrated a room-temperature silicon single-electron transistor memory that consists of ͑i͒ a narrow channel metal-oxide-semiconductor field-effect transistor with a width ͑ϳ10 nm͒ smaller than the Debye screening length of single electron; and ͑ii͒ a nanoscale polysilicon dot ͑ϳ7ϫ7 nm͒ as the floating gate embedded between the channel and the control gate. We have observed that storing one electron on the floating gate can significantly screen the channel from the potential on the
more » ... ntrol gate, leading to a discrete shift in the threshold voltage, a staircase relationship between the charging voltage and the threshold shift, and a self-limiting charging process. © 1997 American Institute of Physics. ͓S0003-6951͑97͒00907-8͔ Floating-gate metal-oxide-semiconductor ͑MOS͒ memories based on single-electron effect are very attractive, due to the possibility of a quantized threshold voltage shift, quantized charging voltage to create the shift, small device size, and fast charging time. However, fabrication of such devices demands cutting-edge nanotechnology. To relax fabrication requirement, the single-electron MOS memories ͑SEMMs͒ fabricated previously have nonconventional structures, such as a channel made of polysilicon or a floating gate consisting of many isolated silicon nanocrystals, but these devices suffer fluctuation in the device's dimension and performance. 1,2 For example, the nature of the polysilicon channel SEMM prevents a precise control of the actual transistor channel width, the floating-gate size, and tunnel barrier thickness. 1 In the multinanocrystal floating-gate device, the size of the silicon nanocrystals have a broad distribution. 2 All of these statistical variations lead to a large fluctuation in the threshold voltage shift and in the charging voltage, therefore, they are unsuitable to large scale integration. Here we present a single electron MOS memory having a narrow channel and a nanoscale floating gate with a wellcontrolled dimension. We report that the charging of a single electron to the floating gate will lead to, at room temperature, a quantized threshold voltage shift, a discrete charging voltage, and a self-limiting charging process. As depicted in Fig. 1 , there are two key features of our SEMM. ͑1͒ The width of silicon metal-oxide-semiconductor field-effect transistor ͑MOSFET͒ channel is narrower than the Debye screening length of a single electron; and ͑2͒ the floating gate is a nanoscale square ͑hence, called dot͒ to significantly increase single-electron charging energy as well as the quantization energy. Otherwise, the device is similar to an ordinary floating-gate MOS memory. The narrow channel ensures that storing a single electron on the floating gate is sufficient to screen the entire channel ͑i.e., the full channel width͒ from the potential on the control gate, leading to a significant threshold voltage shift. A small floating gate is used to significantly increase electron quantum energy ͑due to small size͒ and electron charging energy ͑due to small capacitance͒, hence, the threshold voltage shift and the charging voltage become discrete and well separated at room temperature. Note that the control gate in our device is very long, but the device's threshold is determined by the section where the floating gate is located. In fabrication, the narrow silicon channels with an initial channel thickness of 35 nm and an initial width varying from 25 to 120 nm were fabricated on silicon on insulator ͑SOI͒ using electron beam lithography and reactive ion etching ͑RIE͒. Next, square-shaped floating gates made of polysilicon were deposited and patterned using a second level e-beam lithography and RIE. The gate has a size almost the same as the channel width and an initial thickness of 11 nm. Then a 18 nm oxide was thermally grown, which would consume silicon, reducing the thickness of the polysilicon dot by about 9 nm, and the lateral size of the dot and the silicon channel width by about 18 nm. A plasma-enhanced chemical-vapor deposition oxide of 22 nm thick was deposited giving the total control oxide of 40 nm. A 3 m-long polysilicon gate that covers the small floating gate and part of the narrow channel was deposited and patterned. After making final contacts, the devices were sintered to reduce the interface states. Many fabrications described here are similar to our previous work. [3] [4] [5] Note that in our devices, no tunnel oxide was intentionally added between the channel and polysilicon floating gate. The reason is twofold: ͑1͒ to allow fast charging and ͑2͒ to minimize the potential difference between the channel and the floating dot during the charging process, so that the Coulomb blockade effect can regulate the number of electrons a͒ Electronic mail: chou@ee.umn. edu FIG. 1. Schematic of a single-electron MOS memory that has a narrow silicon channel and a nanoscale polysilicon dot as the floating gate. The cross-section view illustrates the floating gate and the channel region.
doi:10.1063/1.118236 fatcat:7dpg2v42rfhk7dhhnzwbvxia6q