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Functional errors and bugs inadvertently introduced at the RTL stage of the design process are responsible for the largest fraction of silicon IC re-spins. Thus, comprehensive functional verification is the key to reduce development costs and to deliver a product in time. The increasing demands for verification led to an increase in FPGA-based tools that perform emulation. These tools can run at much higher operating frequencies and achieve higher coverage than simulation. However, an importantdoi:10.1109/ipdpsw.2016.95 dblp:conf/ipps/KourfaliS16 fatcat:zwf5mbw7u5ejtif4b27bu4kptq