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Multi-Story Power Distribution Networks for GPUs
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)
High-performance chips require many power pins to support large currents, which increases fabrication cost, limits scalability, and degrades power efficiency. Multi-story serial power distribution networks (PDNs) are a promising approach to reducing pin counts and power losses. We study the feasibility of 2-story PDNs for graphics processing units (GPUs). These PDNs use either an auxiliary off-chip regulator or integrated on-die supercapacitors to stabilize the virtual rail voltage. Static SIMTdoi:10.3850/9783981537079_0900 fatcat:lc5kpe7ezndhtctpkrfrvvjwxi