Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

<span title="">2014</span> <i title="International Digital Organization for Scientific Information (IDOSI)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/pcffws5cpnbi5npocbyumjhaci" style="color: black;">International Journal of Engineering</a> </i> &nbsp;
Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip (SoC) due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a NoC based system. This paper presents reliability and performance evaluation of two main kinds of fault-aware routing algorithms, deterministic and
more &raquo; ... , used in NoC architectures. The investigated methods have a multi-level structure for faulttolerance and therefore, each level can be separately evaluated. To demonstrate the effectiveness of these methods, we propose an analytical approach for reliability assessment based on combinatorial reliability models to show the effect of fault-aware routing algorithms on overall NoC reliability. However, for performance evaluation, we conduct extensive simulations on different applications.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5829/idosi.ije.2014.27.04a.01">doi:10.5829/idosi.ije.2014.27.04a.01</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ncwqlw6zxvefvpukfubz4as4pq">fatcat:ncwqlw6zxvefvpukfubz4as4pq</a> </span>
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