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Static power model for CMOS and FPGA circuits
2021
IET Computers & Digital Techniques
In Ultra-Low-Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time-consuming Spice simulations are used to measure the static power consumption. Herein, a technology-independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time. It is shown that active area only is not a good indicator for static power consumption, hence in this model,
doi:10.1049/cdt2.12021
fatcat:3kury4xftnabpib3dkkbq5jgcy