Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

T. Phatrapornnant, M.J. Pont
2006 IEEE transactions on computers  
All rights reserved INFORMATION TO ALL U SE R S The quality of this reproduction is d ep endent upon the quality of the copy submitted. In the unlikely event that the author did not sen d a com plete manuscript and there are m issing p a g es, th e se will be noted. Also, if material had to be removed, a note will indicate the deletion. Abstract This thesis is concerned with the development o f single-processor embedded systems in which there are requirements for both low CPU energy consumption
more » ... and low levels of task jitter. The focus o f the work is on ways in which dynamic voltage scaling (DVS) techniques can be incorporated in simple time-triggered scheduling algorithms in order to meet these constraints. Following a review o f previous work in this area, a presentation is made which illustrates the impact o f a naive application o f DVS in a system incorporating a timetriggered co-operative (TTC) scheduler. Novel algorithms (TTC-jDVS, TTC-jDVS2) are then introduced which more successfully integrate TTC and DVS techniques. These algorithms involve: (i) changes to system timer settings when the frequency is altered; (ii) use o f a form o f "sandwich delay" to reduce the impact o f changes to the scheduler overhead which arise as a result o f frequency changes, and (iii) execution of jitter-sensitive tasks at a fixed operating frequency. First o f all, I would like to thank my supervisor Dr. Michael J. Pont who has guided and encouraged me over the last four years. I have enjoyed working with him and am very grateful for all his wonderful support. Without him, this thesis would not have been possible.
doi:10.1109/tc.2006.29 fatcat:uxl6rxhwg5dvfhspyodwii67eq