A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is
As feature sizes continue to shrink and integration densities continue to increase, interconnect delays have become a critical bottleneck in 2D NoC performance. The upcoming decades will require a change from mere transistor scaling to novel packaging architectures such as the vertical integration of chips referred as 3D integration. 3D silicon integration technologies have provided new opportunities for NoC architecture design in SoCs enabling the design of complex and highly interconnecteddoi:10.5120/ijca2017914875 fatcat:c7wzcnumq5ca3evxthiourc66m