The IC packaging industry is now being driven by mobile devices, a market where cost and size are key. Going to finer line widths and spacings allows a reduction in the number of layers making up a multilayer chip package, giving a reduction in the cost and height profile of the device, as well as improved signal latency. Embedding conductors within a dielectric film makes it possible to plate to the required thickness without lateral growth of the traces. Using an ablative laser process to do

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... his avoids the financial and environmental costs of lithographic processes. A method for the 3D structuring of dielectric films with pads, traces and vias with a resolution down to 2µm is described. The set up uses a frequency tripled solid state laser to raster scan a binary mask, which is subsequently imaged onto a substrate with a maximum image field of 20x20mm. This offers performance and cost advantages over alternative methods.