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On the effectiveness of register moves to minimise post-pass unrolling in software pipelined loops
2012
2012 International Conference on High Performance Computing & Simulation (HPCS)
Software pipelining is a powerful technique to expose fine-grain parallelism, but it results in variables staying alive across more than one kernel iteration. It requires periodic register allocation and is challenging for code generation: the lack of a reliable solution currently restricts the applicability of software pipelining. The classical software solution that does not alter the computation throughput consists in unrolling the loop a posteriori [12], [11] . However, the resulting
doi:10.1109/hpcsim.2012.6266972
dblp:conf/ieeehpcs/BachirCT12
fatcat:2gwcmkisarcvxbpiu7v635rtey