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Methodology and system for practical formal verification of reactive hardware
[chapter]
1994
Lecture Notes in Computer Science
M/tking formal verification a practicality in industrial environments is still difficult. The capacity of most verification tools is too small, their integration in a design process is difficult and the methodology that should guide their usage is unclear. This paper describes a step-by-step methodology which was developed for the practical application of formal verification. The methodology was successfully realized in a production environment of hardware design. The realization involved the
doi:10.1007/3-540-58179-0_53
fatcat:x6eal3hlmff25kt7a4hakua2uq