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Compact physical models for multilevel interconnect crosstalk in a gigascale SoC
IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings.
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For the first time, compact physical models are derived for multilevel interconnect crosstalk that is induced by inter and intra-level near and far aggressors. It is shown that Crosstalk can be prohibitively large if interconnects have a small resistance. For a given case study, it is shown that crosstalk can be reduced from 0.80V dd to 0.25V dd by increasing line resistance from 45Ω/cm to 270Ω/cm, which increases latency by 230% and 30% for nonbuffered and optimally-buffered interconnects, respectively.
doi:10.1109/soc.2003.1241492
fatcat:yygrdwllmbhydacfb5u2ox56fm