Algorithm level recomputing using allocation diversity: a register transfer level approach to time redundancy-based concurrent error detection

Kaijie Wu, R. Karri
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. The authors show that the
more » ... osed scheme provides very good CED capability with very low area overhead. Index Terms-Algorithm level recomputing, concurrent error detection, fault tolerance, high-level synthesis, register transfer level. 0278-0070/02$17.00 © 2002 IEEE Kaijie Wu (S'01) received the B.E. degree from Xidian University, China, in 1996, and the M.S. degree from the University of Science and Technology of China, in 1999. He is currently working toward the Ph.D. degree from Polytechnic University, Brooklyn, NY. His research interests include computer-aided design and high-level synthesis of fault tolerant design, high-speed hardware architectures of cryptographic protocols, and algorithms.
doi:10.1109/tcad.2002.801110 fatcat:tq6iahfqwbccfir4pqtqjuz7re