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We propose a novel data budget-based approach to dynamically control the average power consumption of Serial RapidIO endpoint controllers in FPGAs. The key concept of the approach is to not only perform clock-gating on the FPGAinternal components of the communication controller, but to disable the multi-gigabit transceivers during idle periods. The clock synchronization, inherent to serial interfaces, enables us to omit the often needed periodic link sensing, and only enable the controllerdoi:10.1109/fccm.2012.26 dblp:conf/fccm/SchmidHT12 fatcat:wbqpjw75ozazhbysek2px3offe