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Area-optimized design of SOT-MRAM
2020
IEICE Electronics Express
In this letter, we present a new structure of spin-orbit torque magnetic random access memory (SOT-MRAM) for area optimization. Based on the observation of SOT-MRAM layout that the metal line can be added in the horizontal direction without increasing the cell area, the proposed design optimizes the metal line routing direction as well as biasing conditions for read and write operations. Implemented with a 45-nm CMOS technology, the proposed design achieves cell area reduction of 42% (23%)
doi:10.1587/elex.17.20200314
fatcat:jp2gcphwsrgapemcycc3wlr74y